As more and more MEMS devices become smaller and smaller, it will be useful to have a MEMS device where two different CMOS substrates to provide electronic circuits are connected to a MEMS substrate. This is particularly useful as more functionality can be added to the CMOS substrate at the same time keeping the form factor small. Furthermore, performance and reliability of the MEMs device can be improved by lowering interconnect parasitic resistance, capacitance and inductance. Combining a CMOS, MEMS and another CMOS in one package that is vertically stacked results in a smaller package with reduced requirements for board area or “real estate.” This stacking structure is also beneficial when the upper CMOS die is smaller than the lower CMOS die and MEMS die such as triple die stack, using CMOS as a cap.
Accordingly, it is desired to have a MEMS device that addresses the requirements of more functionality at the same time keeping the form factor small as well as improvement in the device function and reliability by lowering interconnect parasitics such as resistance, capacitance and inductance. The present invention addresses such a need.